Cache and interconncect architectures in multiprocessord
/ edited by Michel Dubois and Shreekant S. Thakkar
Cache and interconncect architectures in multiprocessord
المؤلف
/ edited by Michel Dubois and Shreekant S. Thakkarطبع 1
0-7923-9074-1
قائمة
شناسنامه
العنوان واسم المؤلف
Cache and interconncect architectures in multiprocessord / / edited by Michel Dubois and Shreekant S. Thakkarبيانات النشر
بوستون : : Kluwer Academic Publishers، 1990مالمواصفات الشكلية
xii, 276 p.؛ ; 24 cm؛ : ill,l.الموضوع
Computer networks protocolsCongresses
Multiprocessors
Congresses
Computer network architectures
Congresses
المعرّفات المضافة
Dubois, Nichel, 1953-، نویسنده .
Thakkar, S. S، نویسنده .
Interconnect architectures in multiprocessors، نویسنده .
Thakkar, S. S، نویسنده .
Interconnect architectures in multiprocessors، نویسنده .
اللغة
انگلیسیرقم الاسترجاع
المؤتمر:
انگليسي.
Papers presented at a workshop titledCache and Intercommect Architectures in Multiprocessors, held in Eilat, Israel, May 25-26, 1989.
Includes biliographical references and index.
Papers presented at a workshop titledCache and Intercommect Architectures in Multiprocessors, held in Eilat, Israel, May 25-26, 1989.
Includes biliographical references and index.
