Unitied methods for VLSI simulation and test generation
/ by Kwang - Ting Cheng and Vishwani D. Agrawal
Unitied methods for VLSI simulation and test generation
طبع 1
0-7923-9025-3
قائمة
شناسنامه
المدخل الرئيسي
Cheng, Kwang - Ting، نویسندهالعنوان واسم المؤلف
Unitied methods for VLSI simulation and test generation / / by Kwang - Ting Cheng and Vishwani D. Agrawalبيانات النشر
بوستون : : Kluwer Academic Publishers، 1989مالمواصفات الشكلية
xii, 148 p.؛ ; 24 cm؛ : fig..الموضوع
Integrated CircuitsVery large scale integration
Design and construction
Computer - aided design
Integrated Circuits
Large scale integration
Testing
Integrated Circuits
Vey large scale integation
Computer simulation
مسلسل
(The Kluwer international series in engineering and computer science؛ )المعرّفات المضافة
Agrawal, Vishwani D, 1943 -، نویسنده .
اللغة
انگلیسیرقم الاسترجاع
المؤتمر:
انگليسي.
Includes bibliographical references and index.
Includes bibliographical references and index.
