Unitied methods for VLSI simulation and test generation
/ by Kwang - Ting Cheng and Vishwani D. Agrawal
Unitied methods for VLSI simulation and test generation
نسخه 1
0-7923-9025-3
فهرست
شناسنامه
سرشناسه
Cheng, Kwang - Ting، نویسندهعنوان و نام پدیدآور
Unitied methods for VLSI simulation and test generation / / by Kwang - Ting Cheng and Vishwani D. Agrawalمشخصات نشر
بوستون : : Kluwer Academic Publishers، 1989ممشخصات ظاهری
xii, 148 p.؛ ; 24 cm؛ : fig..موضوع
Integrated CircuitsVery large scale integration
Design and construction
Computer - aided design
Integrated Circuits
Large scale integration
Testing
Integrated Circuits
Vey large scale integation
Computer simulation
فروست
(The Kluwer international series in engineering and computer science؛ )شناسه های افزوده
Agrawal, Vishwani D, 1943 -، نویسنده .
زبان
انگلیسیشماره بازیابی
کنگره:
انگليسي.
Includes bibliographical references and index.
Includes bibliographical references and index.
