Cache and interconncect architectures in multiprocessord
/ edited by Michel Dubois and Shreekant S. Thakkar
Cache and interconncect architectures in multiprocessord
Author
/ edited by Michel Dubois and Shreekant S. ThakkarEdition 1
0-7923-9074-1
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شناسنامه
Title and Author
Cache and interconncect architectures in multiprocessord / / edited by Michel Dubois and Shreekant S. ThakkarPublication Details
بوستون : : Kluwer Academic Publishers، 1990مPhysical Description
xii, 276 p.؛ ; 24 cm؛ : ill,l.Subject
Computer networks protocolsCongresses
Multiprocessors
Congresses
Computer network architectures
Congresses
Added Identifiers
Dubois, Nichel, 1953-، نویسنده .
Thakkar, S. S، نویسنده .
Interconnect architectures in multiprocessors، نویسنده .
Thakkar, S. S، نویسنده .
Interconnect architectures in multiprocessors، نویسنده .
Language
انگلیسیRetrieval Number
Congress:
انگليسي.
Papers presented at a workshop titledCache and Intercommect Architectures in Multiprocessors, held in Eilat, Israel, May 25-26, 1989.
Includes biliographical references and index.
Papers presented at a workshop titledCache and Intercommect Architectures in Multiprocessors, held in Eilat, Israel, May 25-26, 1989.
Includes biliographical references and index.
