Unitied methods for VLSI simulation and test generation

Name: Unitied methods for VLSI simulation and test generation
Author: / by Kwang - Ting Cheng and Vishwani D. Agrawal

Author

/ by Kwang - Ting Cheng and Vishwani D. Agrawal

کتابخانه مرکزی دانشگاه تهران

Edition 1

0-7923-9025-3

list

Digital Version(s)

شناسنامه

Main Entry

Cheng, Kwang - Ting، نویسنده

Title and Author

Unitied methods for VLSI simulation and test generation / / by Kwang - Ting Cheng and Vishwani D. Agrawal

Publication Details

بوستون : : Kluwer Academic Publishers، 1989م

Physical Description

xii, 148 p.؛ ; 24 cm؛ : fig..

Subject

Integrated Circuits
Very large scale integration
Design and construction
Computer - aided design
Integrated Circuits
Large scale integration
Testing
Integrated Circuits
Vey large scale integation
Computer simulation

series

(The Kluwer international series in engineering and computer science؛ )

Added Identifiers

Agrawal, Vishwani D, 1943 -، نویسنده .

Language

انگلیسی

Retrieval Number

Congress:

انگليسي.

Includes bibliographical references and index.

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