Hierarchical modeling for VLSI circuit testing

Name: Hierarchical modeling for VLSI circuit testing
Author: / by Debashis Bhattacharya, John P. Hayes

Author

Edition 1

0-7923-9058-x

list

شناسنامه

Main Entry

Bhattacharya, Debashis، نویسنده

Title and Author

Hierarchical modeling for VLSI circuit testing / / by Debashis Bhattacharya, John P. Hayes

Publication Details

بوستون : : Kluwer Academic Publishers، 1990م

Physical Description

x, 159p.؛ ; 24 cm؛ : ill..

Subject

Integrated Circuits
Vey large scale integration
Testing
Integrated Circuits
Vey large scale integation
Computer simulation

series

(The Kluwer international series in engineering and computer science. VLSI, computer architecture and digital signal processing؛ )

Added Identifiers

Hayes, John P (John Patrick), 1944-، نویسنده .

Language

انگلیسی

Retrieval Number

Congress:

Notes

انگليسي.

Includes bibliographical references (p.[147] - 155) and index.